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TL16C750E Datasheet(PDF) 40 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 59 page  40 TL16C750E SLLSF10 – DECEMBER 2019 www.ti.com Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) MCR[7:5] can be modified only when EFR[4] is set, that is, EFR[4] is a write enable. 9.5.7 Modem Control Register (MCR) The MCR controls the interface with the modem, data set, or peripheral device that is emulating the modem. Table 12 shows modem control register bit settings. Table 12. MCR Bit Settings(1) BIT BIT SETTINGS 0 0 = Force DTR output to inactive (high) 1 = Force DTR output to active (low). In loopback controls MSR[5] 1 0 = Force RTS output to inactive (high) 1 = Force RTS output to active (low) In loopback controls MSR[4] If Auto-RTS is enabled the RTS output is controlled by hardware flow control 2 0 Disables the FIFORdy register 1 Enable the FIFORdy register In loopback controls MSR[6] 3 0 = Forces the INT output to high-impedance state 1 = Forces the INT output to the active state In loopback controls MSR[7] 4 0 = Normal operating mode 1 = Enable local loopback mode (internal) In this mode, the MCR[3:0] signals are looped back into MSR[3:0] and the TX output is looped back to the RX input internally 5 0 = Disable Xon Any function 1 = Enable Xon Any function 6 0 = No action 1 = Enable access to the TCR and TLR registers 7 0 = Divide by one clock input 1 = Divide by four clock input (1) The primary inputs RI, CD, CTS, and DSR are all active low, but their registered equivalents in the MSR and MCR (in loopback) registers are active high. 9.5.8 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 13 shows modem status register bit settings. Table 13. MSR Bit Settings(1) BIT BIT SETTINGS 0 Indicates that CTS input (or MCR[1] in loopback) has changed state. Cleared on a read. 1 Indicates that DSR input (or MCR[0] in loopback) has changed state. Cleared on a read. 2 Indicates that RI input (or MCR[2] in loopback) has changed state from low to high. Cleared on a read. 3 Indicates that CD input (or MCR[3] in loopback) has changed state. Cleared on a read. 4 This bit is equivalent to MCR[1] during local loop-back mode. It is the complement to the CTS input. 5 This bit is equivalent to MCR[0] during local loop-back mode. It is the complement to the DSR input. 6 This bit is equivalent to MCR[2] during local loop-back mode. It is the complement to the RI input. 7 This bit is equivalent to MCR[3] during local loop-back mode. It is the complement to the CD input. |
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