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TL16C750E Datasheet(PDF) 4 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 59 page  4 TL16C750E SLLSF10 – DECEMBER 2019 www.ti.com Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NAME NO. A0 28 I Address bit 0 select. Internal registers address selection. Refer to Figure 30 for register address map. A1 27 I Address bit 1 select. Internal registers address selection. Refer to Figure 30 for register address map. A2 26 I Address bit 2 select. Internal registers address selection. Refer to Figure 30 for register address map. CD 40 I Carrier detect (active low). A low on these pins indicates that a carrier has been detected by the modem. CS 11 I Chip select. When CS is low, this input enables the ACE. When this input is high, the ACE remains inactive. When MODE is pulled low for "IOR Unused" mode, this will be pulled low and the state of IOW is read to determine if the transaction is a read or a write CTS 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 (ΔCTS) of the modem status register indicates that CTS has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter. D0, D1, D2 D3, D4, D5, D6, D7 43, 44, 45 46, 47, 2, 3, 4 I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. DSR 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 (ΔDSR) of the modem status register indicates DSR has changed levels since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes levels, an interrupt is generated. DTR 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active level by setting the DTR bit of the modem control register. DTR is placed in the inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit. These pins can also be used in the RS-485 mode to control an external RS-485 driver or transceiver. MODE 10 I Interface mode select pin. This pin must be tied to VCC or to GND. If MODE is pulled to VCC, IOR is used in communication. If MODE is pulled to GND, IOR is NOT used for communication. Only the state of IOW is sampled when CS is toggled low to determine if the transaction is a read or a write. In this mode, IOR must be connected to VCC VSS 18 GND Power Reference INT 30 O Interrupt. When active, INT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. IOR 19 I Read inputs. When IOR is active (low) while the ACE is selected, the CPU is allowed to read status information or data from ACE register. IOW 16 I Write input (active low strobe). A valid low level on IOW transfers the contents of the data bus (D0 through D7) from the external CPU to an internal register that is defined by address bits A0 through A2. NC 1, 5, 6, 9, 12, 13, 17, 20, 21, 22, 24, 25, 34, 36, 37, 48 No internal connection OP 31 O The state of this pin is defined by the user through the software settings of the MCR register, bit 3. INT is set to active mode and OP to logic 0 when the MCR-3 is set to logic 1. INT is set to the 3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0 RESET 35 I Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input are disabled during reset time. RI 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. RTS 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic RX 7 I Receive data input. During the local loopback mode, this RX input pin is disabled and TX data is internally connected to the UART RX input internally. During normal mode, RX should be held high when no data is being received. This input also can be used in IrDA mode. For more information, see IrDA Overview. RXRDY 29 O Receive ready (active low). RXRDY goes low when the trigger level has been reached or a timeout interrupt occurs. It go high when the RX FIFO is empty or there is an error in RX FIFO. TX 8 O Transmit data. This output is associated with serial transmit data from the TL16C750E device. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input. TXRDY 23 O Transmit ready (active low). TXRDY goes low when there are a trigger level number of spaces available. They go high when the TX buffer is full. VCC 42 PWR Power supply inputs |
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