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TL16C750E Datasheet(PDF) 37 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 59 page  37 TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 9.5.2 Receiver Holding Register (RHR) The receiver section consists of the RHR and the receiver shift register (RSR). The RHR is actually a 128-byte FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location 0 of the FIFO is used to store the characters. If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each character. 9.5.3 Transmit Holding Register (THR) The transmitter section consists of the THR and the transmitter shift register (TSR). The transmit holding register is actually a 128-byte FIFO. The THR receives data and shifts it into the TSR where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, location 0 of the FIFO is used to store the byte. Characters are lost if overflow occurs. 9.5.4 FIFO Control Register (FCR) This is a write-only register which is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signaling. Table 9 shows FIFO control register bit settings. (1) FCR[5 −4] can be modified and enabled only when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced function. Table 9. FCR Bit Settings BIT BIT SETTINGS 0 0 = Disable the transmit and receive FIFOs 1 = Enable the transmit and receive FIFOs 1 0 = No change 1 = Clears the receive FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO. 2 0 = No change 1 = Clears the transmit FIFO and resets its counter logic to 0. Returns to 0 after clearing FIFO. 3 0 = DMA mode 0 1 = DMA mode 1 5:4(1) Sets the trigger level for the TX FIFO: 00 – 16 spaces 01 – 32 spaces 10 – 64 spaces 11 – 120 spaces 7:6 Sets the trigger level for the RX FIFO: 00 – 1 characters 01 – 4 characters 10 – 120 characters 11 – 124 characters |
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