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TL16C750E Datasheet(PDF) 35 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 59 page  TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 35 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Bits represented by the blue shaded cells can only be modified if EFR[4] is enabled, that is, if enhanced functions are enabled. (2) For more register access information, see Figure 30. (3) Read = R; Write = W (4) This register is only accessible when LCR[7] = 1 (5) This register is only accessible LCR[7:5] = 100 (6) This register is only accessible when LCR = 1011 1111 (0xBF) Table 8. TL16C750E Internal Registers(1) (2) ADDRESS [A2:A0] REGISTER R/W (3) ACCESS CONSIDERATION BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 RHR R LCR[7] = 0 bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 THR W bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 DLL(4) RW LCR[7] = 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 1 IER RW LCR[7] = 0 CTS# Interrupt enable(1) 0 RTS# Interrupt enable(1) 0 Xoff Interrupt enable(1) 0 Sleep mode(1) 0 Modem status interrupt 0 RX line status interrupt 0 THR empty interrupt 0 RX data available interrupt 0 DLH(4) RW LCR[7] = 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 0 IIR R LCR[7] = 0 FCR(0) 0 FCR(0) 0 CTS# / RTS# 0 Xoff 0 Interrupt priority bit 2 0 Interrupt priority bit 1 0 Interrupt priority bit 0 0 Interrupt status 1 FCR W RX trigger level 0 RX trigger level 0 TX trigger level(1) 0 TX trigger level(1) 0 DMA mode select 0 Resets TX FIFO 0 Resets RX FIFO 0 Enable FIFOs 0 AFR(5) RW LCR[7:5] = 100 DLY2 0 DLY1 0 DLY0 0 RCVEN 1 485LG 0 485EN 0 IREN 0 RES 0 EFR(6) RW LCR[7:0] = 10111111 Auto CTS# 0 Auto RTS# 0 Special character detect 0 Enable enhanced functions 0 S/W flow control bit 3 0 S/W flow control bit 2 0 S/W flow control bit 1 0 S/W flow control bit 0 0 0 1 1 LCR RW None DLAB & EFR enable 0 Break control bit 0 Sets parity 0 Parity type select 1 Parity enable 1 No. of stop bits 1 Word length 0 Word length 1 1 0 0 MCR RW LCR[7:0] ≠ 10111111 1x / 4x clock(1) 0 TCR & TLR enable(1) 0 Xon any(1) 0 Enable loopback 0 INT enable 0 FIFORDY enable 0 RTS# 0 DTR# 0 Xon1(6) RW LCR[7:0] = 10111111 bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 1 bit 2 1 bit 1 1 bit 0 1 1 0 1 LSR R LCR[7:0] ≠ 10111111 Error in RX FIFO 0 THR & TSR empty 1 THR empty 1 Break interrupt 0 Framing error 0 Parity error 0 Overrun error 0 Data in receiver 0 Xon2(6) RW LCR[7:0] = 10111111 bit 7 1 bit 6 1 bit 5 1 bit 4 0 bit 3 1 bit 2 1 bit 1 1 bit 0 1 |
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