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TL16C750E Datasheet(PDF) 28 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 59 page  XTAL 1 XTAL 2 Input Clock MCR[7] = 0 MCR[7] = 1 Reference Clock Internal Baud Rate Clock For Transmitter and Receiver Prescaler Logic (Divide By 1) Prescaler Logic (Divide By 4) Baud Rate Generator Logic DLL, DLH, DLF 1 when MCR[7] is set to 0 after reset Prescaler = 4 when MCR[7] is set to 1 after reset Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate × baud divider) 28 TL16C750E SLLSF10 – DECEMBER 2019 www.ti.com Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 9.3.13 Programmable Baud Rate Generator with Fractional Divisor The TL16C750E UART contains a programmable baud generator that divides reference clock by a divisor in the range between 1 and (216 − 1) and a decimal resolution of 1/64. The output frequency of the baud rate generator is 8× or 16× the baud rate, depending on the value of DLF[7]. An additional divide-by-4 prescaler is also available and can be selected by MCR[7] as shown in the following. The formula for the divisor is: Where 'baud divider' is either 8 or 16, depending on the value of DLF[7]. By default, DLF[7] = 0, which corresponds to a baud divider of 16 and Figure 26 shows the internal prescaler and baud rate generator circuitry. Figure 26. Prescaler and Baud Rate Generator Block Diagram DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled, because no baud clock is generated. The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal with frequency 1.8432 and 3.072 MHz, respectively. |
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