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TL16C750E Datasheet(PDF) 27 Page - Texas Instruments |
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TL16C750E Datasheet(HTML) 27 Page - Texas Instruments |
27 / 59 page Processor IOWIOR / LSR IER 0 THR RHR 0 0 0 27 TL16C750E www.ti.com SLLSF10 – DECEMBER 2019 Product Folder Links: TL16C750E Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 9.3.11 Polled Mode Operation In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 25 shows polled mode operation. Figure 25. FIFO Polled Mode Operation 9.3.12 Break and Timeout Conditions An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 × programmed word length) + 12 bits and there is at least one byte stored in the RX FIFO. When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6]. |
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