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TL16C750E Datasheet(PDF) 26 Page - Texas Instruments

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Part # TL16C750E
Description  TL16C750E UART with 128-Byte FIFO
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TL16C750E Datasheet(HTML) 26 Page - Texas Instruments

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Processor
IOWIOR
/
IER
IIR
0
THR
RHR
0
0
0
INT
26
TL16C750E
SLLSF10 – DECEMBER 2019
www.ti.com
Product Folder Links: TL16C750E
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Copyright © 2019, Texas Instruments Incorporated
9.3.9 Interrupts
The TL16C750E UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability.
The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to
an interrupt generation. The IER also can disable the interrupt system by clearing bits 0 to 3, 5 to 7. When an
interrupt is generated, the interrupt identification register (IIR) indicates that an interrupt is pending and provides
the type of interrupt through IIR[5
−0]. Table 4 summarizes the interrupt control functions.
Table 4. Interrupt Control Functions
IIR[5–0]
PRIORITY
LEVEL
INTERRUPT
TYPE
INTERRUPT SOURCE
INTERRUPT RESET METHOD
000001
None
None
None
None
000110
1
Receiver line
status
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE < PE < BI: All erroneous characters are
read from the RX FIFO. OE: Read LSR
001100
2
RX timeout
Stale data in RX FIFO
Read RHR
000100
2
RHR interrupt
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
Read RHR
000010
3
THR interrupt
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level (FIFO
enable)
Read IIR or a write to the THR
001000
4
Modem status
MSR[3:0] != 0
Read MSR
010000
5
Xoff interrupt
Receive Xoff character or
characters/special character
Receive Xon character or characters/Read of
IIR
100000
6
CTS, RTS
RTS pin or CTS pin change state from
active (low) to inactive (high)
Read IIR
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the RX
FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the RX FIFO is empty, then LSR[4–2] is all 0.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the ISR.
9.3.10 Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is 1), the processor is informed of the status of the receiver and
transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register
(LSR) to see if any interrupt needs to be serviced. Figure 24 shows interrupt mode operation.
Figure 24. Interrupt Mode Operation


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