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TL16C750E Datasheet(PDF) 19 Page - Texas Instruments

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Part # TL16C750E
Description  TL16C750E UART with 128-Byte FIFO
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TL16C750E Datasheet(HTML) 19 Page - Texas Instruments

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TX
RX
128-Byte TX FIFO
128-Byte RX FIFO
UART Registers
Baud
Rate
Generator
UART
TX
CTS
OP, DTR
DSR, RI, CD
RTS
RX
Data Bus
Interface
A2 to A0
D7 to D0
CS
IOR
IOW
INT
TXRDY
RXRDY
RESET
XTAL1
XTAL2
Crystal
Oscillator
Buffer
19
TL16C750E
www.ti.com
SLLSF10 – DECEMBER 2019
Product Folder Links: TL16C750E
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Copyright © 2019, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
The TL16C750E UART is pin-compatible with the TL16C550D UART in the PFB package. It provides more
enhanced features. All additional features are provided through a special enhanced features register.
The TL16C750E UART performs serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The
complete status of the TL16C750E UART can be read at any time during functional operation by the processor.
The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the
RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 128-byte receive FIFO and
transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, software flow control and hardware flow control capabilities.
9.2 Functional Block Diagrams
Figure 18. TL16C750E Functional Block Diagram


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