CD4016 datasheet(1/12 Pages) ONSEMI

Part #	CD4016

Description	Quad Analog Switch/Quad Multiplexer

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Manufacturer	ONSEMI [ON Semiconductor]

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March, 2000 – Rev. 3

1

Publication Order Number:

MC14016B/D

MC14016B

Quad Analog Switch/

Quad Multiplexer

The MC14016B quad bilateral switch is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. Each MC14016B consists of four independent

switches capable of controlling either digital or analog signals. The

quad bilateral switch is used in signal gating, chopper, modulator,

demodulator and CMOS logic implementation.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Linearized Transfer Characteristics

• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical

• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved

transfer characteristic design causes more parasitic coupling

capacitance than CD4016)

• For Lower R

ON, Use The HC4016 High–Speed CMOS Device or

The MC14066B

• This Device Has Inputs and Outputs Which Do Not Have ESD

Protection. Antistatic Precautions Must Be Taken.

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage Range

– 0.5 to +18.0

V

Vin, Vout

Input or Output Voltage Range

(DC or Transient)

– 0.5 to VDD + 0.5

V

Iin

Input Current (DC or Transient)

per Control Pin

±10

mA

ISW

Switch Through Current

±25

mA

PD

Power Dissipation,

per Package (Note 3.)

500

mW

TA

Ambient Temperature Range

– 55 to +125

°C

Tstg

Storage Temperature Range

– 65 to +150

°C

TL

Lead Temperature

(8–Second Soldering)

260

°C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

A

= Assembly Location

WL or L

= Wafer Lot

YY or Y

= Year

WW or W = Work Week

Device

Package

Shipping

ORDERING INFORMATION

MC14016BCP

PDIP–14

2000/Box

MC14016BD

SOIC–14

55/Rail

MC14016BDR2

SOIC–14

2500/Tape & Reel

MC14016BF

SOEIAJ–14

See Note 1.

MARKING

DIAGRAMS

1

14

PDIP–14

P SUFFIX

CASE 646

MC14016BCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

1

14

14016B

AWLYWW

SOEIAJ–14

F SUFFIX

CASE 965

1

14

MC14016B

AWLYWW

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

MC14016BFEL

SOEIAJ–14

See Note 1.

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