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EDS1232CASE Datasheet(PDF) 1 Page - Elpida Memory |
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EDS1232CASE Datasheet(HTML) 1 Page - Elpida Memory |
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1 / 53 page  Document No. E0351E30 (Ver. 3.0) Date Published October 2004 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2003-2004 DATA SHEET 128M bits SDRAM EDS1232CASE (4M words × 32 bits) Description The EDS1232CASE is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 90-ball FBGA ( µBGA). Features • 2.5V power supply • Clock frequency: 100MHz (max.) • Single pulsed /RAS • ×32 organization • 4 banks can operate simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length (BL): 1, 2, 4, 8 and full page • 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8, full page) Interleave (BL = 1, 2, 4, 8) • Programmable /CAS latency (CL): 2, 3 • Byte control by DQM • Refresh cycles: 4096 refresh cycles/64ms • 2 variations of refresh Auto refresh Self refresh • FBGA(µBGA) package with lead free solder (Sn-Ag-Cu) Pin Configurations /xxx indicate active low signal. DQ26 1 A B C D E F G H J K L M N P R 23456789 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 /CS DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 /RAS (Top view) DQM1 NC NC /CAS /WE DQM0 VDDQ DQ8 VSS VDD DQ7 VSSQ VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 DQ13 DQ15 VSS VDD DQ0 DQ2 90-ball FBGA ( µBGA) Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A11 BA0, BA1 DQ0 to DQ31 /CS /RAS /CAS /WE DQM0 to DQM3 CKE CLK VDD VSS VDDQ VSSQ NC |
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