EDS1232AATA-75L-E datasheet(40/53 Pages) ELPIDA

Part #	EDS1232AATA-75L-E

Description	128M bits SDRAM (4M words x 32 bits)

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Manufacturer	ELPIDA [Elpida Memory]

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EDS1232AATA

Data Sheet E0386E40 (Ver. 4.0)

40

Bank active command interval

1. Same bank: The interval between the two bank active commands must be no less than tRC.

2. In the case of different bank active commands: The interval between the two bank active commands must be no

less than tRRD.

CLK

Command

Address

BS

Bank 0

Active

ACT

ROW

ACT

ROW

Bank 0

Active

tRC

Bank Active to Bank Active for Same Bank

CLK

Command

Address

BS

Bank 0

Active

Bank 3

Active

ACT

ROW:0

ACT

ROW:1

tRRD

Bank Active to Bank Active for Different Bank

Mode register set to Bank active command interval

The interval between setting the mode register and executing a bank active command must be no less than lMRD.

CLK

Command

Address

Mode

Register Set

Bank

Active

MRS

lMRD

ACT

BS & ROW

OPCODE

Mode register set to Bank active command interval

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EDS1232AATA-75L-E Datasheet(PDF) 40 Page - Elpida Memory

EDS1232AATA-75L-E Datasheet(HTML) 40 Page - Elpida Memory

Similar Part No. - EDS1232AATA-75L-E

Similar Description - EDS1232AATA-75L-E

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