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EDS1232AATA-75L-E Datasheet(PDF) 26 Page - Elpida Memory |
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EDS1232AATA-75L-E Datasheet(HTML) 26 Page - Elpida Memory |
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26 / 53 page  EDS1232AATA Data Sheet E0386E40 (Ver. 4.0) 26 Power-up Sequence Power-up sequence The SDRAM should be goes on the following sequence with power up. The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence. The CKE and DQM is driven to high between power stabilizes and the initialization sequence. This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these pins go high before power up, the large current flows from these pins to VDD through the diodes. Initialization sequence When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device. VDD, VDDQ Power up sequence Initialization sequence 100 µs 0 V Low Low Low CKE, DQM CLK /CS, DQ 200 µs Power stabilize Power-up sequence and Initialization sequence |
Similar Part No. - EDS1232AATA-75L-E |
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Similar Description - EDS1232AATA-75L-E |
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