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EDS1232AATA-75L-E Datasheet(PDF) 19 Page - Elpida Memory |
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EDS1232AATA-75L-E Datasheet(HTML) 19 Page - Elpida Memory |
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19 / 53 page  EDS1232AATA Data Sheet E0386E40 (Ver. 4.0) 19 Current state /CS /RAS /CAS /WE Address Command Operation Notes Write recovering H × × × × DESL Nop → Enter row active after tDPL L H H H × NOP Nop → Enter row active after tDPL L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA Start read, Determine AP 8 L H L L BA, CA, A10 WRIT/ WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL Write recovering H × × × × DESL Nop → Enter precharge after tDPL with auto L H H H × NOP Nop → Enter precharge after tDPL precharge L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3, 8 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H × REF/SELF ILLEGAL L L L L OPCODE MRS ILLEGAL Refresh H × × × × DESL Nop → Enter idle after tRC L H H H × NOP/BST Nop → Enter idle after tRC L H H L × READ/READA ILLEGAL L H L H × ACT/PRE/PALL ILLEGAL L H L L × REF/SELF/MRS ILLEGAL Mode register H × × × × DESL Nop → Enter idle after tRSC accessing L H H H × NOP Nop → Enter idle after tRSC L H H L × BST ILLEGAL L H L H × READ/READA ILLEGAL L L L L × ACT/PRE/PLL/ REF/SELF/MRS ILLEGAL Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data BA: Bank Address, CA: Column Address, RA: Row Address Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down mode. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus trun around, and/or write recovery requirements. 9. Must mask preceding data which don’t satisfy tDPL. 10. Illegal if tRRD is not satisfied. |
Similar Part No. - EDS1232AATA-75L-E |
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Similar Description - EDS1232AATA-75L-E |
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