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EDS1232AATA-75L-E Datasheet(PDF) 11 Page - Elpida Memory |
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EDS1232AATA-75L-E Datasheet(HTML) 11 Page - Elpida Memory |
11 / 53 page ![]() EDS1232AATA Data Sheet E0386E40 (Ver. 4.0) 11 Command Operation Mode register set command (/CS, /RAS, /CAS, /WE) The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through A11 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this command, the Synchronous DRAM cannot accept any other commands. /WE /CAS /RAS /CS CKE CLK H Add A10 BA0, BA1 (Bank select) Mode Register Set Command Activate command (/CS, /RAS = Low, /CAS, /WE = High) The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling. /WE /CAS /RAS /CS CKE CLK H Add A10 BA0, BA1 Row Row (Bank select) Row Address Strobe and Bank Activate Command |
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