edd2508akta-5 datasheet(9/48 Pages) ELPIDA

Part #	EDD2508AKTA-5

Description	256M bits DDR SDRAM (32M words x 8 bits, DDR400)

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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9 / 48 page

EDD2508AKTA-5

Preliminary Data Sheet E0349E60 (Ver. 6.0)

9

Timing Parameter Measured in Clock Cycle

Number of clock cycle

tCK

5ns

Parameter

Symbol

min.

max.

Unit

Write to pre-charge command delay (same bank)

tWPD

4 + BL/2

—

tCK

Read to pre-charge command delay (same bank)

tRPD

BL/2

—

tCK

Write to read command delay (to input all data)

tWRD

2 + BL/2

—

tCK

Burst stop command to write command delay

tBSTW

3

—

tCK

Burst stop command to DQ High-Z

tBSTZ

3

tCK

Read command to write command delay

(to output all data)

tRWD

3 + BL/2

—

tCK

Pre-charge command to High-Z

tHZP

3

tCK

Write command to data in latency

tWCD

1

tCK

Write recovery

tWR

3

—

tCK

DM to data in latency

tDMD

0

tCK

Mode register set command cycle time

tMRD

2

—

tCK

Self refresh exit to non-read command

tSNR

15

—

tCK

Self refresh exit to read command

tSRD

200

—

tCK

Power down entry

tPDEN

1

tCK

Power down exit to command input

tPDEX

1

—

tCK

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EDD2508AKTA-5 Datasheet(PDF) 9 Page - Elpida Memory

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