EDD2508AKTA-5 datasheet(33/48 Pages) ELPIDA

Part #	EDD2508AKTA-5

Description	256M bits DDR SDRAM (32M words x 8 bits, DDR400)

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Manufacturer	ELPIDA [Elpida Memory]

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33 / 48 page

EDD2508AKTA-5

Preliminary Data Sheet E0349E60 (Ver. 6.0)

33

A Write command to the consecutive Read command interval: To interrupt the write operation

Destination row of the consecutive read

command

Bank

address

Row address State

Operation

1. Same

Same

ACTIVE

DM must be input 1 cycle prior to the read command input to prevent from being

written invalid data. In case, the read command is input in the next cycle of the

write command, DM is not necessary.

2. Same

Different

—

—*

1

3. Different

Any

ACTIVE

DM must be input 1 cycle prior to the read command input to prevent from being

written invalid data. In case, the read command is input in the next cycle of the

write command, DM is not necessary.

IDLE

—*

1

Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write

operation in this case.

WRITE to READ Command Interval (Same bank, same ROW address)

in0

in1

in2

out0 out1 out2 out3

CK

/CK

DM

DQ

Command

t1

t0

t2

t3

t4

t5

t6

t7

t8

BL = 4

CL = 3

DQS

Data masked

1 cycle

READ

NOP

WRIT

High-Z

CL=3

[WRITE to READ delay = 1 clock cycle]

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EDD2508AKTA-5 Datasheet(PDF) 33 Page - Elpida Memory

EDD2508AKTA-5 Datasheet(HTML) 33 Page - Elpida Memory

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