EDD2508AKTA-5 datasheet(31/48 Pages) ELPIDA

Part #	EDD2508AKTA-5

Description	256M bits DDR SDRAM (32M words x 8 bits, DDR400)

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Manufacturer	ELPIDA [Elpida Memory]

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EDD2508AKTA-5

Preliminary Data Sheet E0349E60 (Ver. 6.0)

31

A Read command to the consecutive Write command interval with the BST command

Destination row of the consecutive write

command

Bank

address

Row address State

Operation

1. Same

Same

ACTIVE

Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the

consecutive write command can be issued.

2. Same

Different

—

Precharge the bank to interrupt the preceding read operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive write command can be issued. See ‘A read command to the

consecutive precharge interval’ section.

3. Different

Any

ACTIVE

Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the

consecutive write command can be issued.

IDLE

Precharge the bank independently of the preceding read operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive write command can be issued.

out0 out1

in0

in1

in2

in3

CK

/CK

DM

DQ

Command

t1

t0

t2

t3

t4

t5

t6

t7

t8

BL = 4

CL = 3

DQS

OUTPUT

INPUT

tBSTW (

≥ tBSTZ)

High-Z

READ

WRIT

BST

NOP

tBSTZ (= CL)

READ to WRITE Command Interval

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EDD2508AKTA-5 Datasheet(PDF) 31 Page - Elpida Memory

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