EDD2508AKTA-5 datasheet(29/48 Pages) ELPIDA

Part #	EDD2508AKTA-5

Description	256M bits DDR SDRAM (32M words x 8 bits, DDR400)

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Manufacturer	ELPIDA [Elpida Memory]

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EDD2508AKTA-5

Preliminary Data Sheet E0349E60 (Ver. 6.0)

29

A Write command to the consecutive Write command Interval

Destination row of the consecutive write

command

Bank

address

Row address State

Operation

1. Same

Same

ACTIVE

The consecutive write can be performed after an interval of no less than 1 cycle to

interrupt the preceding write operation.

2. Same

Different

—

Precharge the bank to interrupt the preceding write operation. tRP after the

precharge command, issue the ACT command. tRCD after the ACT command, the

consecutive write command can be issued. See ‘A write command to the

consecutive precharge interval’ section.

3. Different

Any

ACTIVE

The consecutive write can be performed after an interval of no less than 1 cycle to

interrupt the preceding write operation.

IDLE

Precharge the bank without interrupting the preceding write operation. tRP after

the precharge command, issue the ACT command. tRCD after the ACT command,

the consecutive write command can be issued.

;;

;

inA0 inA1 inB0 inB1 inB2 inB3

CK

/CK

Address

BA

DQ

Command

t0

tn+1

tn

tn+2

tn+3

tn+4

tn+5

tn+6

Bank0

Active

;;;

;

BL = 4

Bank0

NOP

DQS

ACT

NOP

WRIT

Row

Column A

WRIT

Column B

Column = A

Write

Column = B

Write

WRITE to WRITE Command Interval (same ROW address in the same bank)

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EDD2508AKTA-5 Datasheet(PDF) 29 Page - Elpida Memory

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