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EDD2508AKTA-5 Datasheet(PDF) 24 Page - Elpida Memory

Part # EDD2508AKTA-5
Description  256M bits DDR SDRAM (32M words x 8 bits, DDR400)
Download  48 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD2508AKTA-5 Datasheet(HTML) 24 Page - Elpida Memory

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EDD2508AKTA-5
Preliminary Data Sheet E0349E60 (Ver. 6.0)
24
CK
/CK
VTT
VTT
DQS
DQ
CL = 3
Command
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
out0
out1
out2
out3
tRPST
tAC,tDQSCK
READ
NOP
tRPRE
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when
the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst
operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge
of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low
period of DQS is referred as write postamble.
in1
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
BL: Burst length
t1
t0
tn tn+0.5 tn+1
tn+2
tn+3
tn+4
tn+5
in0
ACT
NOP
NOP
NOP
WRITE
tWPRE
tWPRES
;;
;;;
;
;
Row
Column
tRCD
tWPST
Write Operation


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