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EDD2508AKTA-5 Datasheet(PDF) 23 Page - Elpida Memory |
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EDD2508AKTA-5 Datasheet(HTML) 23 Page - Elpida Memory |
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23 / 48 page  EDD2508AKTA-5 Preliminary Data Sheet E0349E60 (Ver. 6.0) 23 Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued. Read operation The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble. out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 CK /CK Address DQS DQ BL = 2 BL = 4 BL = 8 Command CL = 3 BL: Burst length t1 t0 t5 t6 t7 t8 t9 t10 tRCD tRPRE tRPST ACT NOP NOP NOP READ Row Column t11 Read Operation (Burst Length) |
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