EDD2508AKTA-5 datasheet(15/48 Pages) ELPIDA

Part #	EDD2508AKTA-5

Description	256M bits DDR SDRAM (32M words x 8 bits, DDR400)

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Manufacturer	ELPIDA [Elpida Memory]

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EDD2508AKTA-5

Preliminary Data Sheet E0349E60 (Ver. 6.0)

15

Function Truth Table

The following tables show the operations that are performed when each command is issued in each state of the

DDR SDRAM.

Current state

/CS

/RAS

/CAS /WE

Address

Command

Operation

Next state

Precharging*

1

H

×

DESL

NOP

ldle

L

H

×

NOP

ldle

L

H

L

×

BST

ILLEGAL*

11

—

L

H

L

H

BA, CA, A10

READ/READA

ILLEGAL*

11

—

L

H

L

BA, CA, A10

WRIT/WRITA

ILLEGAL*

11

—

L

H

BA, RA

ACT

ILLEGAL*

11

—

L

H

L

BA, A10

PRE, PALL

NOP

ldle

L

×

ILLEGAL

—

Idle*

2

H

×

DESL

NOP

ldle

L

H

×

NOP

ldle

L

H

L

×

BST

ILLEGAL*

11

—

L

H

L

H

BA, CA, A10

READ/READA

ILLEGAL*

11

—

L

H

L

BA, CA, A10

WRIT/WRITA

ILLEGAL*

11

—

L

H

BA, RA

ACT

Activating

Active

L

H

L

BA, A10

PRE, PALL

NOP

ldle

L

H

×

REF, SELF

Refresh/

Self refresh*

12

ldle/

Self refresh

L

MODE

MRS

Mode register set*

12

ldle

Refresh

(auto-refresh)*

3

H

×

DESL

NOP

ldle

L

H

×

NOP

ldle

L

H

L

×

BST

ILLEGAL

—

L

H

L

×

ILLEGAL

—

L

×

ILLEGAL

—

Activating*

4

H

×

DESL

NOP

Active

L

H

×

NOP

Active

L

H

L

×

BST

ILLEGAL*

11

—

L

H

L

H

BA, CA, A10

READ/READA

ILLEGAL*

11

—

L

H

L

BA, CA, A10

WRIT/WRITA

ILLEGAL*

11

—

L

H

BA, RA

ACT

ILLEGAL*

11

—

L

H

L

BA, A10

PRE, PALL

ILLEGAL*

11

—

L

×

ILLEGAL

—

Active*

5

H

×

DESL

NOP

Active

L

H

×

NOP

Active

L

H

L

×

BST

ILLEGAL

Active

L

H

L

H

BA, CA, A10

READ/READA

Starting read operation Read/READA

L

H

L

BA, CA, A10

WRIT/WRITA

Starting write

operation

Write

recovering/

precharging

L

H

BA, RA

ACT

ILLEGAL*

11

—

L

H

L

BA, A10

PRE, PALL

Pre-charge

Idle

L

×

ILLEGAL

—

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