EDD1216AATA-5 datasheet(37/48 Pages) ELPIDA

Part #	EDD1216AATA-5

Description	128M bits DDR SDRAM (8M words x 16 bits, DDR400)

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Manufacturer	ELPIDA [Elpida Memory]

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EDD1216AATA-5

Data Sheet E0443E40 (Ver. 4.0)

37

Bank active command interval

Destination row of the consecutive ACT

command

Bank

address

Row address

State

Operation

1. Same

Any

ACTIVE

Two successive ACT commands can be issued at tRC interval. In between two

successive ACT operations, precharge command should be executed.

2. Different

Any

ACTIVE

Precharge the bank. tRP after the precharge command, the consecutive ACT

command can be issued.

IDLE

tRRD after an ACT command, the next ACT command can be issued.

CK

/CK

Command

BA

tRC

Address

ACTV

tRRD

Bank0

Active

Bank3

Active

Bank0

Precharge

Bank0

Active

PRE

ACT

ROW: 0

NOP

ACT

ROW: 1

ROW: 0

Bank Active to Bank Active

Mode register set to Bank-active command interval

The interval between setting the mode register and executing a bank-active command must be no less than tMRD.

CK

/CK

Command

Address

NOP

MRS

ACT

tMRD

Mode Register Set

Bank3

Active

CODE

BS and ROW

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EDD1216AATA-5 Datasheet(PDF) 37 Page - Elpida Memory

EDD1216AATA-5 Datasheet(HTML) 37 Page - Elpida Memory

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