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EDD1216AATA-5 Datasheet(PDF) 32 Page - Elpida Memory

Part # EDD1216AATA-5
Description  128M bits DDR SDRAM (8M words x 16 bits, DDR400)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD1216AATA-5 Datasheet(HTML) 32 Page - Elpida Memory

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EDD1216AATA-5
Data Sheet E0443E40 (Ver. 4.0)
32
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
2. Same
Different
—
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
3. Different
Any
ACTIVE
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
IDLE
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
in0
in1
in2
in3
out2
out0
out1
CK
/CK
DM
DQ
Command
t1
t0
t2
t3
t4
t5
t6
t7
t8
;
;
;;
;;
BL = 4
CL = 3
tWRD (min)
tWTR*
DQS
INPUT
OUTPUT
BL/2 + 2 cycle
WRIT
NOP
NOP
READ
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval


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