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EDD1216AATA-5 Datasheet(PDF) 21 Page - Elpida Memory |
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EDD1216AATA-5 Datasheet(HTML) 21 Page - Elpida Memory |
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21 / 48 page  EDD1216AATA-5 Data Sheet E0443E40 (Ver. 4.0) 21 Operation of the DDR SDRAM Power-up Sequence (1)Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 µs. (3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device. (8) Issue 2 or more auto-refresh commands. (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL. Command EMRS PALL MRS REF 2 cycles (min.) 2 cycles (min.) 200 cycles (min) 2 cycles (min.) 2 cycles (min.) tRP tRFC tRFC PALL MRS REF REF Any command DLL enable DLL reset with A8 = High CK /CK (4) (5) (6) (7) (8) (9) Disable DLL reset with A8 = Low Power-up Sequence after CKE Goes High Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A11 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A11 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters shown in the table bellow are allowed to input to the registers. A2 A1 A0 Burst Length 00 1 2 01 0 4 01 1 8 BT=0 BT=1 2 4 8 A3 0 Sequential 1 Interleave Burst Type A6 A5 A4 CAS Latency 011 3 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 00 0 0 DR LMODE BT BL A8 0No 1 Yes DLL Reset A11 A10 BA1 BA0 0 MRS Mode Register Set [MRS] (BA0 = 0, BA1 = 0) |
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