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EBE51UD8ABFA Datasheet(PDF) 12 Page - Elpida Memory

Part # EBE51UD8ABFA
Description  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBE51UD8ABFA Datasheet(HTML) 12 Page - Elpida Memory

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EBE51UD8ABFA
Data Sheet E0357E50 (Ver. 5.0)
12
Parameter
Symbol
Grade
max.
Unit
Test condition
-5C
2000
Auto-refresh current
IDD5
-4A
1840
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
48
mA
Self Refresh Mode;
CK and /CK at 0V;
CKE
≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
-5C
2560
Operating current
(Bank interleaving)
IDD7
-4A
2400
mA
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
−1
× tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
× tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤VIL (AC) (max.)
H is defined as VIN
≥VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
4-4-4
3-3-3
Unit
CL(IDD)
4
3
tCK
tRCD(IDD)
15
15
ns
tRC(IDD)
55
55
ns
tRRD(IDD)
7.5
7.5
ns
tCK(IDD)
3.75
5
ns
tRAS(min.)(IDD)
40
40
ns
tRAS(max.)(IDD)
70000
70000
ns
tRP(IDD)
15
15
ns
tRFC(IDD)
105
105
ns


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