EBE51UD8ABFA datasheet(11/22 Pages) ELPIDA

Part #	EBE51UD8ABFA

Description	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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11 / 22 page

EBE51UD8ABFA

Data Sheet E0357E50 (Ver. 5.0)

11

DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)

Parameter

Symbol

Grade

max.

Unit

Test condition

-5C

880

Operating current

(ACT-PRE)

IDD0

-4A

760

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

-5C

1000

Operating current

(ACT-READ-PRE)

IDD1

-4A

880

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

-5C

80

Precharge power-down

standby current

IDD2P

-4A

64

mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

-5C

200

Precharge quiet standby

current

IDD2Q

-4A

160

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

-5C

240

Idle standby current

IDD2N

-4A

200

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

-5C

320

IDD3P-F

-4A

280

mA

Fast PDN Exit

MRS(12) = 0

-5C

200

Active power-down

standby current

IDD3P-S

-4A

160

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address bus

inputs are STABLE;

Data bus inputs are FLOATING

Slow PDN Exit

MRS(12) = 1

-5C

520

Active standby current

IDD3N

-4A

480

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

-5C

1520

Operating current

(Burst read operating)

IDD4R

-4A

1200

mA

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

-5C

1520

Operating current

(Burst write operating)

IDD4W

-4A

1200

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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