EBE51UD8ABFA datasheet(1/22 Pages) ELPIDA

Part #	EBE51UD8ABFA

Description	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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Document No. E0357E50 (Ver. 5.0)

Date Published August 2004 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2003-2004

DATA SHEET

512MB Unbuffered DDR2 SDRAM DIMM

EBE51UD8ABFA (64M words

×××× 64 bits, 1 Rank)

Description

The EBE51UD8ABFA is 64M words

× 64 bits, 1 rank

DDR2 SDRAM unbuffered module, mounting 8 pieces

of 512M bits DDR2 SDRAM sealed in FBGA (

µBGA)

package. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 4 bits prefetch-

pipelined architecture. Data strobe (DQS and /DQS)

both for read and write are available for high speed and

reliable data bus design. By setting extended mode

register, the on-chip Delay Locked Loop (DLL) can be

set enable or disable.

This module provides high

density mounting without utilizing surface mount

technology.

Decoupling capacitors are mounted

beside each FBGA (

µBGA) on the module board.

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

Features

• 240-pin socket type dual in line memory module

(DIMM)

 PCB height: 30.0mm

 Lead pitch: 1.0mm

 Lead-free

• 1.8V power supply

• Data rate: 533Mbps/400Mbps (max.)

• 1.8V (SSTL_18 compatible) I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

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