EBE51RD8ABFA

Data Sheet E0402E40 (Ver. 4.0)

14

ODT DC Electrical Characteristics (TC = 0 to +85

°°°°C, VDD, VDDQ = 1.8V ±±±± 0.1V)

(DDR2 SDRAM Component Specification)

Parameter

Symbol

min.

typ.

max.

Unit

Note

Rtt effective impedance value for EMRS (A6, A2)

= 0, 1; 75 Ω

Rtt1(eff)

60

75

90

Ω

1

Rtt effective impedance value for EMRS (A6, A2)

= 1, 0; 150 Ω

Rtt2(eff)

120

150

180

Ω

1

Deviation of VM with respect to VDDQ/2

∆VM

−3.75



+3.75

%

1

Note: 1. Test condition for Rtt measurements.

Measurement Definition for Rtt(eff)

Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.

VIH(AC), and VDDQ values defined in SSTL

_18.

VIH(AC)

− VIL(AC)

I(VIH(AC))

− I(VIL(AC))

Rtt(eff) =

Measurement Definition for VM

Measure voltage (VM) at test pin (midpoint) with no load.

2

× VM

VDDQ

∆VM =

× 100%

− 1

OCD Default Characteristics (TC = 0 to +85

°°°°C, VDD, VDDQ = 1.8V ±±±± 0.1V)

(DDR2 SDRAM Component Specification)

Parameter

min.

typ.

max.

Unit

Notes

Output impedance

12.6

18

23.4

Ω

1

Pull-up and pull-down mismatch

0



4

Ω

1, 2

Output slew rate

1.5



4.5

V/ns

3, 4

Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT

−VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and VDDQ−280mV.

Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV;

VOUT/IOL must be less than 23.4

Ω for values of VOUT between 0V and 280mV.

2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and

voltage.

3. Slew rate measured from VIL(AC) to VIH(AC).

4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate

as measured from AC to AC. This is guaranteed by design and characterization.

Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)

Parameter

Symbol

Pins

min.

max.

Unit

Notes

Input capacitance

CI1

Address, /RAS, /CAS,

/WE, /CS, CKE, ODT

2.5

3.5

pF

1

Input capacitance

CI2

CK, /CK

2

3

pF

2

Data and DQS input/output

capacitance

CO

DQ, DQS, /DQS, DM, CB

3

4

pF

3

Notes: 1. Register component specification.

2. PLL component specification.

3. DDR2 SDRAM component specification.