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M5M5256DP-45LL Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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M5M5256DP-45LL Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
4 / 7 page ![]() MITSUBISHI LSIs 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI ELECTRIC M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL '97.4.7 4 (2) READ CYCLE (3) WRITE CYCLE Symbol Parameter tCR Read cycle time Address access time Unit ns ns ns ns ns ns ns ns ns Limits ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) ta(A) -70LL, XL AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted ) (1) MEASUREMENT CONDITIONS Chip select access time Output enable access time Output disable time after /S high Output disable time after /OE high Output enable time after /S low Output enable time after /OE low Data valid time after address Max Min Input pulse level···················VIH=2.4V,VIL=0.6V Input rise and fall time··········5ns Reference level····················VOH=VOL=1.5V Output loads·························Fig.1,CL=30pF (-45LL,-45XL ) CL=50pF (-55LL,-55XL ) CL=100pF (-70LL,-70XL ) CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) 55 5 5 10 Min 55 55 30 20 20 Max 45 5 5 10 Min 45 45 25 15 15 Max -45LL, XL -55LL, XL 70 5 5 10 70 70 35 25 25 Symbol Parameter Unit ns ns ns ns ns ns ns ns ns ns ns ns Limits Write cycle time Write pulse width Address setup time Address setup time with respect to /W high Chip select setup time Data setup time Data hold time Write recovery time Output disable time from /W low Output disable time from /OE high Output enable time from /W high Output enable time from /OE low Max Min -70LL, XL -45LL, XL -55LL, XL 20 20 Max 55 40 0 50 50 25 0 0 5 5 Min 15 15 Max 45 35 0 40 40 20 0 0 5 5 Min tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) 25 25 70 50 0 65 65 30 0 0 5 5 Vcc DQ CL Fig.1 Output load 1.8k Ω 990 Ω (Including scope and JIG) |
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