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LT6650 Datasheet(PDF) 10 Page - Linear Technology |
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LT6650 Datasheet(HTML) 10 Page - Linear Technology |
10 / 12 page ![]() LT6650 10 6650f APPLICATIO S I FOR ATIO Figure 11. Worst-Case 0 °C to 70°C Hysteresis Figure 12. Worst-Case –40 °C to 85°C Hysteresis VOUT. RB must be within the following range for proper operation (the optimal value depends greatly on the direc- tion and magnitude of the load current): RB > |VS – VOUT|/(200µA + 0.4/RG) RB < |VS – VOUT|/(15µA + 0.4/RG) Hysteresis Due to various mechanical stress mechanisms inherent to integrated-circuit packaging, internal offsets may not pre- cisely recover from variations that occur over tempera- ture, and this effect is referred to as hysteresis. Proprietary manufacturing steps minimize this hysteresis, though some small residual error can occur. Hysteresis measure- ments for the LT6650 can be seen in Figures 11 and 12. Figure 11 presents the worst-case data taken on parts subjected to thermal cycling between 0 °C to 70°C, while Figure 12 shows data for –40 °C to 85°C cycling. Units were cycled several times over these temperature ranges and the largest changes are shown. As would be expected, the parts cycled over the higher temperature extremes exhibit a broader hysteresis distribution. The worst hys- teresis measurements indicate voltage shifts of less than 1000ppm (0.1%) from their initial value. Limits of Operation The LT6650 is a robust bipolar technology part. ESD clamp diodes are integrated into the design and are depicted in the Simplified Schematic for reference. Diodes are included between the GND pin and the IN, OUT, and FB pins to prevent reverse voltage stress on the device. Unusual modes of operation that forward-bias any these diodes should limit current to 10mA to avoid permanent damage to the device. The LT6650 is fabricated using a relatively high-voltage process, allowing any pin to inde- pendently operate at up to 20V with respect to GND. The part does not include any over voltage protection mecha- nisms; therefore caution should be exercised to avoid inadvertent application of higher voltages in circuits in- volving high potentials. DISTRIBUTION (ppm) –400 2 3 6 5 4 400 6650 F11 1 0 –200 0 200 600 LIGHT COLUMNS 0 °C TO 25°C DARK COLUMNS 70 °C TO 25°C DISTRIBUTION (ppm) –1000 2 3 6 5 4 500 6650 F12 7 1 0 –500 1000 250 –750 –250 0 750 LIGHT COLUMNS –40 °C TO 25°C DARK COLUMNS 85 °C TO 25°C |
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