CS8421

12

DS641PP1

3. GENERAL DESCRIPTION

The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter.

The digital audio data is input and output through configurable 3-wire serial ports. The digital audio in-

put/output ports offer Left Justified, Right Justified, and I²S serial audio formats. The CS8421 also sup-

ports a TDM mode which allows multiple channels of digital audio data on one serial line. A bypass mode

allows the data to be passed directly to the output port without sample rate conversion.

The CS8421 does not require a control port interface, helping to speed design time by not requiring the

user to develop software to configure the part. Pins that are sensed after reset allow the part to be con-

figured. See “Reset, Power Down, and Start-up” on page 32.

Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR),

digital mixing consoles, high quality D/A, effects processors and computer audio systems.

Figure 5 and Figure 6 show the supply and external connections to the CS8421.

4. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT

A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the at-

tached device through the MS_SEL, SAIF, and SAOF pins. Table 1, Table 2, and Table 3 show the pin

functions and their corresponding settings. The following parameters are adjustable:

•

Master or slave.

•

Master clock (MCLK) ratios of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master mode).

•

Audio data resolution of 16, 20, 24, or 32-bits.

•

Left or right justification of the data relative to left/right clock (LRCK) as well as I²S.

Figure 7, Figure 8, and Figure 9 show the input/output formats available.

In master mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin mas-

ter clock.

In slave mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI

master clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough

serial clocks are present in each phase to clock all of the data bits.

ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to

64*Fso. In TDM slave mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s con-

nected together. In TDM master mode, OSCLK is set to 256*Fso

5. MODE SELECTION

The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes

of operation. After reset the resistor value and condition (VL or GND) are sensed. This operation will take

approximately 4

µs to complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be mut-

ed until the mode detection sequence has completed. After this, if all clocks are stable, SRC_UNLOCK

will be brought low when audio output is valid and normal operation will occur. Table 1, Table 2, and

Table 3 show the pin functions and their corresponding settings. If the 1.0 k

Ω option is selected for

MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a direct connection to VL

or GND as appropriate.

The resistor attached to each mode selection pin should be placed physically close to the CS8421. The

end of the resistor not connected to the mode selection pins should be connected as close as possible to

VL and GND to minimize noise. Table 1, Table 2, and Table 3 show the pin functions and their corre-

sponding settings.