CS8421

DS641PP1

3

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

2. TYPICAL CONNECTION DIAGRAMS

................................................................................. 10

3. GENERAL DESCRIPTION ..................................................................................................... 12

4. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT ........................................................ 12

5. MODE SELECTION ................................................................................................................ 12

6. SAMPLE RATE CONVERTER (SRC) .................................................................................... 15

6.1 Clocking ........................................................................................................................... 15

6.2 Data Resolution and Dither ............................................................................................. 15

6.3 SRC Locking and Varispeed ........................................................................................... 15

6.4 Bypass Mode ................................................................................................................... 16

6.5 Muting .............................................................................................................................. 16

6.6 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................... 16

6.7 Master Clock .................................................................................................................... 17

6.8 Time Division Multiplexing (TDM) Mode .......................................................................... 18

7. PIN DESCRIPTIONS

........................................................................................................ 20

7.1 TSSOP Pin Descriptions

.............................................................................................. 21

7.2 QFN Pin Descriptions ..................................................................................................... 22

8. PERFORMANCE PLOTS

.............................................................................................. 23

9. APPLICATIONS .................................................................................................................... 32

9.1 Reset, Power Down, and Start-up ................................................................................... 32

9.2 Power Supply, Grounding, and PCB layout ..................................................................... 32

10. PACKAGE DIMENSIONS ................................................................................................... 33

11. REVISION HISTORY ........................................................................................................... 35

LIST OF FIGURES

Figure 1. Non-TDM Slave Mode Timing.......................................................................................... 8

Figure 2. TDM Slave Mode Timing .................................................................................................8

Figure 3. Non-TDM Master Mode Timing........................................................................................ 9

Figure 4. TDM Master Mode Timing ............................................................................................... 9

Figure 5. Typical Connection Diagram, Master and Slave Modes ................................................ 10

Figure 6. Typical Connection Diagram, No External Master Clock ............................................... 11

Figure 7. Serial Audio Interface Format - I²S ................................................................................ 14

Figure 8. Serial Audio Interface Format - Left Justified................................................................. 14

Figure 9. Serial Audio Interface Format - Right Justified .............................................................. 14

Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................... 17

Figure 11. TDM Slave Mode Timing Diagram............................................................................... 18

Figure 12. TDM Master Mode Timing Diagram............................................................................. 18

Figure 13. TDM Mode Configuration (All CS8421 outputs are slave) ........................................... 19

Figure 14. TDM Mode Configuration (First CS8421 output is master, all others are slave).......... 19

Figure 15a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz ...................... 23

Figure 15b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ................. 23

Figure 16a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ................... 23

Figure 16b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ................... 23

Figure 17a. Wideband FFT Plot (1Fsi6k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz ................. 23

Figure 17b. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz ...................... 23

Figure 18a. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz .................... 24

Figure 18b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz................... 24

Figure 19a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz................... 24

Figure 19b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz.............. 24

Figure 20a. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz................ 24

Figure 20b. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz................ 24