CS8421-CZZ datasheet(8/36 Pages) CIRRUS

Part #	CS8421-CZZ

Description	32-bit, 192 kHz Asynchronous Sample Rate Converter

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Manufacturer	CIRRUS [Cirrus Logic]

Direct Link	http://www.cirrus.com

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CS8421

8

DS641PP1

SWITCHING SPECIFICATIONS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Parameters

Symbol

Min

Max

Units

RST pin Low Pulse Width

(Note 6)

1

-

ms

XTI Frequency (Note 7)

Crystal

Digital Clock Source

16.384

1.024

27.000

MHz

XTI Pulse Width High/Low

14.8

-

ns

MCLK_OUT Duty Cycle

45

55

%

Slave Mode

I/OSCLK Frequency

-

24.576

MHz

OLRCK High Time

(Note 8)

tlrckh

326

-

ns

I/OSCLK High Time

tsckh

9-

ns

I/OSCLK Low Time

tsckl

9-

ns

I/OLRCK Edge to I/OSCLK Rising

tlcks

6-

ns

OLRCK Rising Edge to OSCLK Rising Edge (TDM)

tfss

5-

ns

I/OSCLK Rising Edge to I/OLRCK Edge

tlckd

5-

ns

OSCLK Rising Edge to OLRCK Falling Edge (TDM)

tfsh

5-

ns

OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid

tdpd

-18

ns

SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge

tds

3-

ns

SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge

tdh

5-

ns

t

ds

OLRCK

(input)

t

dh

t

sckh

t

sckl

t

fsh

t

fss

OSCLK

(input)

TDM_IN

(input)

SDOUT

(output)

MSB

t

dpd

MSB-1

MSB

MSB-1

t

lrckh

t

ds

MSB

t

dh

t

dpd

MSB-1

I/OLRCK

(input)

I/OSCLK

(input)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

t

sckh

t

sckl

t

lcks

t

lckd

Figure 1. Non-TDM Slave Mode Timing

Figure 2. TDM Slave Mode Timing

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CS8421-CZZ Datasheet(PDF) 8 Page - Cirrus Logic

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