SSD1963 datasheet(83/93 Pages) ETC2

Part #	SSD1963

Description	1215KB Embedded Display SRAM LCD Display Controller

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SSD1963

Rev 1.1

P 83/93

Jan 2010

Solomon Systech

13.2.2 Parallel 8080-series Interface Timing

Table 13-6: Parallel 8080-series Interface Timing Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

fMCLK

System Clock Frequency*

1

-

110

MHz

tMCLK

System Clock Period*

1/ fMCLK

-

ns

tPWCSL

Control Pulse High Width Write

Read

13

30

1.5* tMCLK

3.5* tMCLK

-

ns

tPWCSH

Control Pulse Low Width Write (next write cycle)

Write (next read cycle)

Read

13

80

1.5* tMCLK

9* tMCLK

-

ns

tAS

Address Setup Time

1

-

ns

tAH

Address Hold Time

2

-

ns

tDSW

Write Data Setup Time

4

-

ns

tDHW

Write Data Hold Time

1

-

ns

tPWLW

Write Low Time

12

-

ns

tDHR

Read Data Hold Time

1

-

ns

tACC

Access Time

32

-

ns

tPWLR

Read Low Time

36

-

ns

tR

Rise Time

-

0.5

ns

tF

Fall Time

-

0.5

ns

tCS

Chip select setup time

2

-

ns

tCSH

Chip select hold time to read signal

3

-

ns

* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)

Figure 13-3: Parallel 8080-series Interface Timing Diagram (Write Cycle)

t

F

t

R

t

AS

t

CS

AH

t

PWLW

t

DSW

t

DHW

t

IH

V

IL

Valid Data

IH

V

VIL

IH

V

IL

IH

V

VIL

PWCSL

PWCSH

D[17:0]

CS#

D/C#

WR#

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