SSD1963 datasheet(81/93 Pages) ETC2

Part #	SSD1963

Description	1215KB Embedded Display SRAM LCD Display Controller

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Manufacturer	ETC2 [List of Unclassifed Manufacturers]

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SSD1963

Rev 1.1

P 81/93

Jan 2010

Solomon Systech

13.2 MCU Interface Timing

13.2.1 Parallel 6800-series Interface Timing

Table 13-4: Parallel 6800-series Interface Timing Characteristics (Use CS# as clock)

Symbol

Parameter

Min

Typ

Max

Unit

fMCLK

System Clock Frequency*

1

-

110

MHz

tMCLK

System Clock Period*

1/ fMCLK

-

ns

tPWCSH

Control Pulse High Width Write

Read

13

30

1.5* tMCLK

3.5* tMCLK

-

ns

tPWCSL

Control Pulse Low Width Write (next write cycle)

Write (next read cycle)

Read

13

80

1.5* tMCLK

9* tMCLK

-

ns

tAS

Address Setup Time

2

-

ns

tAH

Address Hold Time

2

-

ns

tDSW

Data Setup Time

4

-

ns

tDHW

Data Hold Time

1

-

ns

tPLW

Write Low Time

14

-

ns

tPHW

Write High Time

14

-

ns

tPLWR

Read Low Time

38

-

ns

tACC

Data Access Time

32

-

ns

tDHR

Output Hold time

1

-

ns

tR

Rise Time

-

0.5

ns

tF

Fall Time

-

0.5

ns

* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)

Figure 13-1: Parallel 6800-series Interface Timing Diagram (Use CS# as Clock)

D[17:0]

(WRITE)

D[17:0]

(READ)

E

D/C

R/W

CS#

tPLWR / tPLW

tR

tF

tDHW

tACC

tDHR

Valid Data

tDSW

Valid Data

tAH

tAS

tPWCSH

IH

V

IL

V

OL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

OH

V

tPWCSL

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