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SSD1963 Datasheet(PDF) 74 Page - List of Unclassifed Manufacturers

Part # SSD1963
Description  1215KB Embedded Display SRAM LCD Display Controller
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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SSD1963 Datasheet(HTML) 74 Page - List of Unclassifed Manufacturers

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Solomon Systech
Jan 2010
P 74/93
Rev 1.1
SSD1963
Before enabling PLL, the PLL setting (“0xE2”) have to be configured first. After PLL enabled for 100us, can start to
lock PLL. SSD1963 needed to switch to PLL output as system clock after PLL is locked. The following is the program
sequence.
WRITE COMMAND “0xE0”
WRITE DATA “0x01”
Wait 100us to let the PLL stable
WRITE COMMAND “0xE0”
WRITE DATA “0x03”
WRITE COMMAND “0x01”
* Note : SSD1963 is operating under reference clock before PLL is locked, registers cannot be set faster than half of the
reference clock frequency. For instance, SSD1963 with a 10MHz reference clock is not allowed to be programmed
higher than 5M words/s.
9.68 set_pll_mn
Command
0xE2
Parameters
3
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Command
0
1
1
1
0
0
0
1
0
E2
Parameter 1
1
M7
M6
M5
M4
M3
M2
M1
M0
xx
Parameter 2
1
0
0
0
0
N3
N2
N1
N0
xx
Parameter 3
1
0
0
0
0
0
C2
0
0
xx
Description
Set the MN of PLL
M[7:0] : Multiplier (M) of PLL. (POR = 00101101)
N[3:0] : Divider (N) of PLL. (POR = 0011)
C[2] : Effectuate MN value (POR = 0)
0
Ignore the multiplier (N) and divider (N) values
1
Effectuate the multiplier and divider value
VCO = Reference input clock x (M + 1)
PLL frequency = VCO / (N + 1)
* Note : 250MHz < VCO < 800MHz
For a 10MHz reference clock to obtain 100MHz PLL frequency, user cannot program M = 19 and N = 1. The setting in
this situation is setting M=29 and N=2, where 10 x 30 / 3 = 100MHz.
WRITE COMMAND “0xE2”
WRITE DATA “0x1D”
(M=29)
WRITE DATA “0x02”
(N=2)
WRITE DATA “0x54” (Dummy Byte)


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