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SSD1963 Datasheet(PDF) 50 Page - List of Unclassifed Manufacturers |
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SSD1963 Datasheet(HTML) 50 Page - List of Unclassifed Manufacturers |
50 / 93 page Solomon Systech Jan 2010 P 50/93 Rev 1.1 SSD1963 VT[10:8] : High byte of the vertical total (display + non-display) period in lines (POR = 001) VT[7:0] : Low byte of the vertical total (display + non-display) period in lines (POR = 01111111) VPS[10:8] : High byte of the non-display period in lines between the start of the frame and the first display data in line. (POR = 000) VPS[7:0] : Low byte of the non-display period in lines between the start of the frame and the first display data in line. (POR = 00000100) VPW[6:0] : The vertical sync pulse width (LFRAME) in lines. (POR = 000001) FPS[10:8] : High byte of the vertical sync pulse (LFRAME) start location in lines. (POR = 000) FPS[7:0] : Low byte of the vertical sync pulse (LFRAME) start location in lines. (POR = 00000000) 9.39 set_gpio_conf Command 0xB8 Parameters 2 D/C D7 D6 D5 D4 D3 D2 D1 D0 Hex Command 0 1 0 1 1 1 0 0 0 B8 Parameter 1 1 A7 A6 A5 A4 A3 A2 A1 A0 xx Parameter 2 1 0 0 0 0 0 0 0 B0 xx Description Set the GPIOs configuration. If the GPIOs are not used for LCD, set the direction. Otherwise, they are toggled with LCD signals by 0xC0 – 0xCF. A[7] : GPIO3 configuration (POR = 0) 0 GPIO3 is controlled by host 1 GPIO3 is controlled by LCDC A[6] : GPIO2 configuration (POR = 0) 0 GPIO2 is controlled by host 1 GPIO2 is controlled by LCDC A[5] : GPIO1 configuration (POR = 0) 0 GPIO1 is controlled by host 1 GPIO1 is controlled by LCDC A[4] : GPIO0 configuration (POR = 0) 0 GPIO0 is controlled by host 1 GPIO0 is controlled by LCDC A[3] : GPIO3 direction (POR = 0) 0 GPIO3 is input 1 GPIO3 is output A[2] : GPIO3 direction (POR = 0) 0 GPIO2 is input 1 GPIO2 is output A[1] : GPIO1 direction (POR = 0) 0 GPIO1 is input 1 GPIO1 is output A[0] : GPIO0 direction (POR = 0) 0 GPIO0 is input 1 GPIO0 is output |
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