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SSD1963 Datasheet(PDF) 38 Page - List of Unclassifed Manufacturers

Part # SSD1963
Description  1215KB Embedded Display SRAM LCD Display Controller
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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SSD1963 Datasheet(HTML) 38 Page - List of Unclassifed Manufacturers

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 38 / 93 page
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Solomon Systech
Jan 2010
P 38/93
Rev 1.1
SSD1963
A[4] : Line address order (POR = 0)
This bit controls the display panel’s horizontal line refresh order. The image shown on the display panel is unaffected,
regardless of the bit setting.
0
LCD refresh from top line to bottom line.
1
LCD refresh from bottom line to top line.
A[3] : RGB / BGR order (POR = 0)
This bit controls the RGB data order transferred from the SSD1963’s frame buffer to the display panel.
0
RGB
1
BGR
Figure 9-14: A[3] RGB Order
A[3] = 0
A[3] = 1
Frame Buffer
Display Panel
Frame Buffer
Display Panel
R
G
B
R
G
B
R
G
B
B
G
R
A[2] : Display data latch data (POR = 0)
This bit controls the display panel’s vertical line data latch order. The image shown on the display panel is unaffected,
regardless of the bit setting.
0
LCD refresh from left side to right side
1
LCD refresh from right side to left side
A[1] : Flip Horizontal (POR = 0)
This bit flips the image shown on the display panel left to right. No change is made to the frame buffer.
0
Normal
1
Flipped
Figure 9-15: A[1] Flip Horizontal
A[1]=0,
A[4]=A[2]=A[0]=0
A[1]=1,
A[4]=A[2]=A[0]=0
Frame Buffer
Display Panel
Frame Buffer
Display Panel
1
1
1
1
n
n
n
n
1
m
1
m
1
m
m
1


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