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M5M5256DFP-70VLL-I Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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M5M5256DFP-70VLL-I Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
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4 / 7 page  MITSUBISHI LSIs 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI ELECTRIC M5M5256DFP,VP,RV -70VLL-I,-85VLL-I, -70VXL-I,-85VXL-I '97.4.7 4 (2) READ CYCLE (3) WRITE CYCLE Symbol Parameter tCR Read cycle time Address access time Unit ns ns ns ns ns ns ns ns ns Limits ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A) ta(A) AC ELECTRICAL CHARACTERISTICS (Ta = -40~85°C, Vcc=3.3±0.3V, unless otherwise noted ) (1) MEASUREMENT CONDITIONS Chip select access time Output enable access time Output disable time after /S high Output disable time after /OE high Output enable time after /S low Output enable time after /OE low Data valid time after address Input pulse level···················VIH=2.2V,VIL=0.4V Input rise and fall time··········5ns Reference level····················VOH=VOL=1.5V Output loads·························Fig.1,CL=30pF (-70VLL,-70VXL ) CL=50pF (-85VLL,-85VXL ) CL=5pF (for ten,tdis) Transition is measured ±500mV from steady state voltage. (for ten,tdis) 85 10 10 10 Min 85 85 45 25 25 Max 70 5 5 10 Min 70 70 35 25 25 Max -70VLL, VXL -85VLL, VXL Symbol Parameter Unit ns ns ns ns ns ns ns ns ns ns ns ns Limits Write cycle time Write pulse width Address setup time Address setup time with respect to /W high Chip select setup time Data setup time Data hold time Write recovery time Output disable time from /W low Output disable time from /OE high Output enable time from /W high Output enable time from /OE low -70VLL, VXL -85VLL, VXL 25 25 Max 85 60 0 70 70 35 0 0 10 10 Min 25 25 Max 70 55 0 65 65 30 0 0 5 5 Min tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) Fig.1 Output load (Including scope and JIG) DQ L C 1TTL |
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