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S1D13505 Datasheet(PDF) 50 Page - Epson Company |
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S1D13505 Datasheet(HTML) 50 Page - Epson Company |
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50 / 565 page  Epson Research and Development Page 45 Vancouver Design Center Hardware Functional Specification S1D13505 Issue Date: 01/02/02 X23A-A-001-14 1. If the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the fall- ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. 2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid, whichever one is later. Table 7-2: SH-3 Timing 3.0Va a Two Software WAIT States Required 5.0Vb b One Software WAIT State Required Symbol Parameter Min Max Min Max Units t1 Clock period 15.1 15.1 ns t2 Clock pulse width high 66 ns t3 Clock pulse width low 66 ns t4 A[20:0], M/R#, RD/WR# setup to CKIO 33 ns t5 A[20:0], M/R#, RD/WR# hold from CS# 00 ns t6 BS# setup 44 ns t7 BS# hold 11 ns t8 CSn# setup 44 ns t92 Falling edge RD# to D[15:0] driven 00 ns t10 Rising edge CSn# to WAIT# tri-state 525 2.5 10 ns t111 Falling edge CSn# to WAIT# driven 0150 10 ns t12 CKIO to WAIT# delay 4 20 3.6 12 ns t13 D[15:0] setup to 2nd CKIO after BS# (write cycle) 10 10 ns t14 D[15:0] hold (write cycle) 00 ns t15 D[15:0] valid to WAIT# rising edge (read cycle) 00 ns t16 Rising edge RD# to D[15:0] tri-state (read cycle) 525 2.5 10 ns |
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