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S1D13505 Datasheet(PDF) 82 Page - Epson Company

Part # S1D13505
Description  S1D13505 Embedded RANMAC LCD/CRT Controller
Download  565 Pages
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13505 Datasheet(HTML) 82 Page - Epson Company

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Epson Research and Development
Page 77
Vancouver Design Center
Hardware Functional Specification
S1D13505
Issue Date: 01/02/02
X23A-A-001-14
Figure 7-25: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing
1.
Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2.
t1min = t4min - 14Ts
3.
t4min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
4.
t5min = [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts
5.
t6min = [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
6.
t9min = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
Table 7-23: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing
Symbol
Parameter
Min
Typ
Max
Units
t1
FPFRAME setup to FPLINE pulse trailing edge
note 2
t2
FPFRAME hold from FPLINE pulse trailing edge
14
Ts (note 1)
t3
FPLINE pulse width
9Ts
t4
FPLINE period
note 3
t5
MOD transition to FPLINE pulse trailing edge
1note 4
Ts
t6
FPSHIFT falling edge to FPLINE pulse leading edge
note 5
t7
FPLINE pulse trailing edge to FPSHIFT falling edge
t10 + t11
Ts
t8
FPSHIFT period
4Ts
t9
FPSHIFT falling edge to FPLINE pulse trailing edge
note 6
t10
FPLINE pulse trailing edge to FPSHIFT rising edge
20
Ts
t11
FPSHIFT pulse width high
2Ts
t12
FPSHIFT pulse width low
2Ts
t13
UD[3:0] setup to FPSHIFT falling edge
2Ts
t14
UD[3:0] hold to FPSHIFT falling edge
2Ts
t13
t14
t10
t7
t8
t12
t11
12
FPFRAME
FPLINE
MOD
Sync Timing
FPLINE
FPSHIFT
UD[3:0]
Data Timing
t5
t1
t2
t4
t3
t9
t6


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