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S1D13505 Datasheet(PDF) 58 Page - Epson Company |
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S1D13505 Datasheet(HTML) 58 Page - Epson Company |
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58 / 565 page  Epson Research and Development Page 53 Vancouver Design Center Hardware Functional Specification S1D13505 Issue Date: 01/02/02 X23A-A-001-14 1. If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. 2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of RD0#, RD1# or the first positive edge of CLK after A[20:0], M/R# becomes valid, whichever one is later. Table 7-6: Generic Timing 3.0V 5.0V Symbol Parameter Min Max Min Max Units t1 Clock period 20 20 ns t2 Clock pulse width high 66 ns t3 Clock pulse width low 66 ns t4 A[20:0], M/R# setup to first CLK where CS# = 0 and either RD0#,RD1#,WE0# or WE1# = 0 10 10 ns t5 A[20:0], M/R# hold from rising edge of either RD0#,RD1#,WE0# or WE1# = 0 00 ns t6 CS# hold from rising edge of either RD0#,RD1#,WE0# or WE1# = 0 00 ns t71 Falling edge of either RD0#,RD1#,WE0# or WE1# to WAIT# driven low 0 15010 ns t8 Rising edge of either RD0#,RD1#,WE0# or WE1# to WAIT# tri-state 525 2.5 10 ns t9 D[15:0] setup to third CLK where CS# = 0 and WE0#,WE1# = 0 (write cycle) 10 10 ns t10 D[15:0] hold (write cycle) 00 ns t112 Falling edge RD0#,RD1# to D[15:0] driven (read cycle) 00 ns t12 D[15:0] setup to rising edge WAIT# (read cycle) 00 ns t13 Rising edge of RD0#,RD1# to D[15:0] tri-state (read cycle) 5 25510 ns |
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