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S1D13505 Datasheet(PDF) 30 Page - Epson Company |
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S1D13505 Datasheet(HTML) 30 Page - Epson Company |
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30 / 565 page  Epson Research and Development Page 25 Vancouver Design Center Hardware Functional Specification S1D13505 Issue Date: 01/02/02 X23A-A-001-14 DB[15:0] IO 16-31 C/TS2 Hi-Z These pins are the system data bus. For 8-bit bus modes, unused data pins should be tied to VDD. • For SH-3/SH-4 Bus, these pins are connected to D[15:0]. • For MC68K Bus 1, these pins are connected to D[15:0]. • For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340). • For Generic Bus, these pins are connected to D[15:0]. • For MIPS/ISA Bus, these pins are connected to SD[15:0]. • For Philips PR31500/31700 Bus, these pins are connected to D[31:16]. • For Toshiba TX3912 Bus, pins [15:8] are connected to D[23:16] and pins [7:0] are connected to D[31:24]. • For PowerPC Bus, these pins are connected to D[0:15]. • For PC Card (PCMCIA) Bus, these pins are connected to D[15:0]. See “Host Bus Interface Pin Mapping” for summary. See the respective AC Timing diagram for detailed functionality. WE1# IO 9 CS/TS 2 Hi-Z This is a multi-purpose pin: • For SH-3/SH-4 Bus, this pin inputs the write enable signal for the upper data byte (WE1#). • For MC68K Bus 1, this pin inputs the upper data strobe (UDS#). • For MC68K Bus 2, this pin inputs the data strobe (DS#). • For Generic Bus, this pin inputs the write enable signal for the upper data byte (WE1#). • For MIPS/ISA Bus, this pin inputs the system byte high enable signal (SBHE#). • For Philips PR31500/31700 Bus, this pin inputs the odd byte access enable signal (/CARDxCSH). • For Toshiba TX3912 Bus, this pin inputs the odd byte access enable signal (CARDxCSH*). • For PowerPC Bus, this pin outputs the burst inhibit signal (BI#). • For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal (-CE2). See “Host Bus Interface Pin Mapping” for summary. See the respective AC Timing diagram for detailed functionality. M/R# I 5 C Hi-Z • For Philips PR31500/31700 Bus, this pin is connected to VDD. • For Toshiba TX3912 Bus, this pin is connected to VDD. • For all other busses, this input pin is used to select between the display buffer and register address spaces of the S1D13505. M/R# is set high to access the display buffer and low to access the registers. See Register Mapping. See Table 5-6:, “CPU Interface Pin Mapping,” on page 34. CS# I 4 CHi-Z • For Philips PR31500/31700 Bus, this pin is connected to VDD. • For Toshiba TX3912 Bus, this pin is connected to VDD. • For all other busses, this is the Chip Select input. See Table 5-6:, “CPU Interface Pin Mapping,” on page 34. See the respective AC Timing diagram for detailed functionality. Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # Cell RESET# State Description |
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