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S1D13505 Datasheet(PDF) 14 Page - Epson Company

Part # S1D13505
Description  S1D13505 Embedded RANMAC LCD/CRT Controller
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Manufacturer  EPSON [Epson Company]
Direct Link  http://www.epsondevice.com
Logo EPSON - Epson Company

S1D13505 Datasheet(HTML) 14 Page - Epson Company

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Epson Research and Development
Page 9
Vancouver Design Center
Hardware Functional Specification
S1D13505
Issue Date: 01/02/02
X23A-A-001-14
List of Figures
Figure 3-1:
Typical System Diagram (SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3-2:
Typical System Diagram (SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3-3:
Typical System Diagram (MC68K Bus 1, 16-Bit 68000) . . . . . . . . . . . . . . . . . . . . . 16
Figure 3-4:
Typical System Diagram (MC68K Bus 2, 32-Bit 68030) . . . . . . . . . . . . . . . . . . . . . 16
Figure 3-5:
Typical System Diagram (Generic Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-6:
Typical System Diagram (NEC VR41xx (MIPS) Bus) . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-7:
Typical System Diagram (Philips PR31500/PR31700 Bus) . . . . . . . . . . . . . . . . . . . . 18
Figure 3-8:
Typical System Diagram (Toshiba TX3912 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3-9:
Typical System Diagram (Power PC Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3-10:
Typical System Diagram (PC Card (PCMCIA) Bus) . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5-1:
Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5-3:
External Circuitry for CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 7-1:
SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7-2:
SH-3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 7-3:
MC68000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7-4:
MC68030 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7-5:
PC Card Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 7-6:
Generic Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 7-7:
MIPS/ISA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 7-8:
Philips Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 7-9:
Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 7-10:
Toshiba Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 7-11:
Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 7-12:
Power PC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 7-13:
Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 7-14:
EDO-DRAM Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 7-15:
EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7-16:
EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 7-17:
EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 7-18:
FPM-DRAM Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 7-19:
FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 7-20:
FPM-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 7-21:
FPM-DRAM Self-Refresh Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 7-22:
LCD Panel Power Off / Power On Timing. Drawn with LCDPWR set to active high polarity . . 74
Figure 7-23:
Power Save Status and Local Bus Memory Access Relative to Power Save Mode . . . . . . . . 75
Figure 7-24:
4-Bit Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . 76
Figure 7-25:
4-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . 77
Figure 7-26:
8-Bit Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . 78
Figure 7-27:
8-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . 79
Figure 7-28:
4-Bit Single Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 7-29:
4-Bit Single Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 81


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