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S1D13505 Datasheet(PDF) 98 Page - Epson Company |
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S1D13505 Datasheet(HTML) 98 Page - Epson Company |
98 / 565 page Epson Research and Development Page 93 Vancouver Design Center Hardware Functional Specification S1D13505 Issue Date: 01/02/02 X23A-A-001-14 Figure 7-41: 16-Bit Dual Color Passive LCD Panel A.C. Timing 1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) 2. t1min = t3min - 14Ts 3. t3min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts 4. t5min = [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts 5. t6min = [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts 6. t7min = [((REG[05h] bits [4:0]) + 1)*8 - 11] Ts Table 7-31: 16-Bit Dual Color Passive LCD Panel A.C. Timing Symbol Parameter Min Typ Max Units t1 FPFRAME setup to FPLINE pulse trailing edge note 2 t2 FPFRAME hold from FPLINE pulse trailing edge 14 Ts (note 1) t3 FPLINE period note 3 t4 FPLINE pulse width 9Ts t5 MOD transition to FPLINE pulse trailing edge 1note 4 Ts t6 FPSHIFT falling edge to FPLINE pulse leading edge note 5 t7 FPSHIFT falling edge to FPLINE pulse trailing edge note 6 t8 FPLINE pulse trailing edge to FPSHIFT falling edge t14 + 2 t9 FPSHIFT period 2Ts t10 FPSHIFT pulse width low 1Ts t11 FPSHIFT pulse width high 1Ts t12 UD[7:0], LD[7:0] setup to FPSHIFT falling edge 1Ts t13 UD[7:0], LD[7:0] hold to FPSHIFT falling edge 1Ts t14 FPLINE pulse trailing edge to FPSHIFT rising edge 12 Ts Data Timing FPFRAME t1 t2 t3 t5 t4 FPLINE MOD Sync Timing FPLINE FPSHIFT t7 t6 UD[7:0] LD[7:0] t12 t13 t14 t8 t9 t10 t11 12 |
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