S1D13505 datasheet(97/565 Pages) EPSON

Part #	S1D13505

Description	S1D13505 Embedded RANMAC LCD/CRT Controller

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Manufacturer	EPSON [Epson Company]

Direct Link	http://www.epsondevice.com

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Page 92

Epson Research and Development

Vancouver Design Center

S1D13505

Hardware Functional Specification

X23A-A-001-14

Issue Date: 01/02/02

7.5.9 16-Bit Dual Color Passive LCD Panel Timing

Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP

= Vertical Non-Display Period

= (REG[0Ah] bits [5:0]) + 1

HDP

= Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= Horizontal Non-Display Period

= ((REG[05h] bits [4:0]) + 1)*8Ts

9

VDP

FPLINE

FPSHIFT

UD[7:0], LD[7:0]

FPFRAME

FPLINE

MOD

UD6, LD6

UD5, LD5

UD4, LD4

UD3, LD3

UD2, LD2

UD1, LD1

UD0, LD0

UD7, LD7

MOD

VNDP

* Diagram drawn with 2 FPLINE vertical blank period

1-R1,

241-R1

1-B3,

241-B3

1-G638,

241-G638

1-B1,

241-B 1

1-G4,

241-G 4

1-R639,

241-R639

1-R2,

241-R 2

1-B4,

241-B4

1-G639,

241-G63

1-G2,

241-G2

1-R5,

241-R 5

1-B639,

241-B639

1-B2,

241-B 2

1-G5,

241-G 5

1-R640,

241-R640

1-R3,

241-R 3

1-B5,

241-B5

1-G 640,

241-G640

1-G3,

241-G3

1-R6,

241-R 6

1-B640,

241-B640

1-G1,

241-G1

1-R4,

241-R 4

1-B638,

241-B638

HDP

HNDP

Example timing for a 640x480 panel

LINE 1/241

LINE 2/242

LINE 3/243

LINE 4/244

LINE 239/479 LINE 240/480

LINE 1/241

LINE 2/242

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