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S1D13505 Datasheet(PDF) 95 Page - Epson Company |
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S1D13505 Datasheet(HTML) 95 Page - Epson Company |
95 / 565 page Page 90 Epson Research and Development Vancouver Design Center S1D13505 Hardware Functional Specification X23A-A-001-14 Issue Date: 01/02/02 7.5.8 8-Bit Dual Color Passive LCD Panel Timing Figure 7-38: 8-Bit Dual Color Passive LCD Panel Timing VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)*8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts FPLINE FPSHIFT UD[3:0], LD[3:0] FPFRAME FPLINE MOD MOD * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP HDP VNDP HNDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242 1-R 1 1-G1 1-B1 1-R2 1-G 2 1-B2 1-R 3 1-G3 1-B3 1-R4 1-G4 1-B4 1-R5 1-G5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-R8 1-G8 1-B8 1-B639 1-R640 1-G640 1-B640 241- B639 241- R640 241- G640 241- B640 241-R 1 241-G1 241-B1 241-R 2 241-G2 24 1-B2 241-R3 241-G3 241-B 3 241-R 4 241-G4 241-B 4 241-R5 241-G 5 241-B5 241-R 6 241-G6 241-B6 241-R7 241-G7 241-B7 241-R8 241-G8 241-B8 1-B7 FPDAT7 (UD3) FPDAT6 (UD2) FPDAT5 (UD1) FPDAT4 (UD0) FPDAT3 (LD3) FPDAT2 (UD2) FPDAT1 (UD1) FPDAT0 (UD0) |
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