S1D13505 datasheet(93/565 Pages) EPSON

Part #	S1D13505

Description	S1D13505 Embedded RANMAC LCD/CRT Controller

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Manufacturer	EPSON [Epson Company]

Direct Link	http://www.epsondevice.com

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Page 88

Epson Research and Development

Vancouver Design Center

S1D13505

Hardware Functional Specification

X23A-A-001-14

Issue Date: 01/02/02

7.5.7 8-Bit Dual Monochrome Passive LCD Panel Timing

Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP

= Vertical Non-Display Period

= (REG[0Ah] bits [5:0]) + 1

HDP

= Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= Horizontal Non-Display Period

= ((REG[05h] bits [4:0]) + 1)*8Ts

FPLINE

FPSHIFT

UD[3:0], LD[3:0]

FPFRAME

FPLINE

MOD

UD2

UD1

UD0

LD3

LD2

LD1

LD0

UD3

MOD

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

VDP

1-2

1-6

1-638

1-3

1-7

1-639

1-4

1-8

1-640

241-1

241-5

241-637

241-638

241-639

241-640

1-1

1-5

1-637

HDP

241-2

241-6

241-3

241-7

241-4

241-8

VNDP

HNDP

LINE 1/241

LINE 2/242

LINE 3/243

LINE 4/244

LINE 239/479 LINE 240/480

LINE 1/241

LINE 2/242

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