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S1D13505 Datasheet(PDF) 81 Page - Epson Company |
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S1D13505 Datasheet(HTML) 81 Page - Epson Company |
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81 / 565 page  Page 76 Epson Research and Development Vancouver Design Center S1D13505 Hardware Functional Specification X23A-A-001-14 Issue Date: 01/02/02 7.5 Display Interface 7.5.1 4-Bit Single Monochrome Passive LCD Panel Timing Figure 7-24: 4-Bit Single Monochrome Passive LCD Panel Timing VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1 HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)*8Ts HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts FPLINE FPSHIFT FPFRAME FPLINE MOD MOD * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel UD[3:0] UD2 UD1 UD0 UD3 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 1-2 1-6 1-318 1-3 1-7 1-319 1-4 1-8 1-320 1-1 1-5 1-317 VNDP HDP HNDP |
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