S1D13505 datasheet(67/565 Pages) EPSON

Part #	S1D13505

Description	S1D13505 Embedded RANMAC LCD/CRT Controller

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Manufacturer	EPSON [Epson Company]

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Page 62

Epson Research and Development

Vancouver Design Center

S1D13505

Hardware Functional Specification

X23A-A-001-14

Issue Date: 01/02/02

7.2 Clock Input Requirements

Figure 7-13: Clock Input Requirement

Note

When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).

Table 7-13: Clock Input Requirements for CLKI divided down internally (MCLK = CLKI/2)

Symbol

Parameter

Min

Max

Units

T

OSC

Input Clock Period

12.5

ns

t

PWH

Input Clock Pulse Width High

5.6

ns

t

PWL

Input Clock Pulse Width Low

5.6

ns

t

f

Input Clock Fall Time (10% - 90%)

5ns

t

r

Input Clock Rise Time (10% - 90%)

5ns

Table 7-14: Clock Input Requirements for CLKI

Symbol

Parameter

Min

Max

Units

T

OSC

Input Clock Period

25

ns

t

PWH

Input Clock Pulse Width High

11.3

ns

t

PWL

Input Clock Pulse Width Low

11.3

ns

t

f

Input Clock Fall Time (10% - 90%)

5ns

t

r

Input Clock Rise Time (10% - 90%)

5ns

t

PWL

t

PWH

t

f

tr

T

OSC

V

IH

VIL

10%

90%

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